1. Field of the Invention
The present invention relates to a waveform shaping circuit and a digital signal analyzing apparatus using the same and, more particularly, to a digital signal waveform shaping circuit for waveform-shaping an input digital signal and outputting a shaped digital signal and a digital signal analyzing apparatus, such as a logic analyzer or an error measuring apparatus, for analyzing a data signal to be measured input in synchronism with a clock signal by using the digital signal waveform shaping circuit.
2. Description of the Related Art
In general, in the above digital signal analyzing apparatus, when a digital signal received from an external circuit is analyzed, a waveform shaping circuit using a comparator is conventionally utilized not to perform wrong binary determination caused by an offset and noise components superposed on a digital signal.
In the waveform shaping circuit of this type, an operating point of a comparator used in the waveform shaping circuit must be set to be an ideal and stable operating point free from the offset of an input digital signal and an influence of noise. For this reason, the following conventional methods are used:
(1) a technique of manually setting a threshold value level of the comparator in an optimal state while an output waveform of the comparator is monitored; PA0 (2) a technique of inputting an input digital signal to the comparator through a capacitor; and PA0 (3) a technique of manually changing a DC average level of the input digital signal into a predetermined level using a level shifter to input the digital signal to the comparator.
However, according to the techniques (1) and (3), the manual setting operation of the operating point is cumbersome, and the setting operation must be performed every time the level or offset of the input signal is changed.
According to the technique (2), since the offset voltage of the digital signal input to the comparator is changed in accordance with a mark ratio (a ratio of the number of all generated bits to the number of marks included in the bits) of the input digital signal, waveform shaping is not reliably performed at a fixed threshold value
For this reason, another technique of inputting an intermediate voltage between the high- "H" and low- "L" level voltages of an input digital signal to the comparator as a threshold value may be used. However, according to this technique, when the input digital signal has a very high frequency (several GHz), the in-phase input range of the comparator is extremely narrow (e.g., .+-.1 V). When the offset voltage of the input digital signal exceeds the in-phase input range, the comparator is saturated, and a normal waveform shaping operation cannot be performed.
A digital analyzing apparatus such as a logic analyzer or an error (rate) measuring apparatus using the above waveform shaping circuit is generally arranged as shown in FIG. 22.
That is, a data signal to be measured input to an input terminal 1 and a reference voltage Vr from a reference voltage generator 2 are input to a comparator 3, and a binary digital signal from which waveform distortion or a noise component are removed by the comparator 3 is input to the data input terminal (to be referred to as a D terminal) of a discriminator 4 constituted by a D flip-flop.
A clock signal input to an input terminal 5 is input to the clock terminal (to be referred to as a CP terminal) of the discriminator 4 through a variable delay circuit 6.
Therefore, binary discrimination of the digital signal from the comparator 3 is performed at a rise timing of the cock signal input to the discriminator 4, the determination output and the clock signal are input to a data signal analyzer 7, and a predetermined data analysis is performed.
However, since the level of the data signal to be measured input to the input terminal 1 and the phase of the clock signal are not known, before the normal data analyzing operation, the value of the reference voltage and a delay amount of the clock signal must be set to be optimal values with respect to the data signal to be measured in advance.
For this reason, in a conventional technique, a data signal to be measured shown in FIG. 23A is displayed on an oscilloscope, and the reference voltage Vr is adjusted to be positioned at an almost center point (point having a maximum noise margin of an eye-pattern) of the amplitude of the data s gnal to be measured. Thereafter, an output signal from the comparator 3 shown in FIG. 23B and a clock signal shown in FIG. 23C are displayed on a two-channel oscilloscope, and a delay amount of the variable delay circuit 6 is manually adjusted such that the rise timing (discrimination timing of the discriminator 4 of the clock signal is positioned at an almost intermediate point (having a maximum phase margin) between state transition points I and II of the digital signal.
When the delay amount is manually adjusted as described above, the delay amount depends on individual differences of operators, thereby varying the analysis result.
When the adjustment is to be performed by observing a waveform using an oscilloscope, not only connections between devices are cumbersome, but the waveform of a signal is distorted by connecting the oscilloscope to cause an erroneous operation.
For this reason, a method of connecting a monitor terminal for observing a waveform is may be used. However, waveform observing equipment such as an oscilloscope must be prepared as usual. This is very inconvenient.